Difference Between SAP-I and SAP-II

SAP stands for Simple As Possible computer. It is the basic model of an micro-computer. It can perform all the basic functionalities of an microprocessor but has an limited, small and simple set of instructions. It's main purpose is to show how an computer operates without burying you into unnecessary details.

Attribute	SAP-I	SAP-II
Counter	0H to FH	0000H to FFFFH
Opcode	4-bit	8-bit
Address	8-bit	16-bit
Registers	B-register only	B,C and Temp register
I/O ports	2	4
W-bus	8-bit	16-bit
Display	Binary Display	Hexa-Decimal Display
No. of Instruction	5	42
Logical Operations	cannot be performed	can be performed
Memory	16 Byte RAM	62 KB RAM and 2 KB ROM

Basic Direct Memory Access Operation and data tranfers

Direct Memory Access (DMA) :

The DMAC (Direct Memory Access Controller) allows the devices to read/write from/to the memory location without the use of processor. They are used in Sound cards, Video cards, Disk controllers, etc.

An Basic Direct Memory Access operation goes like,

1. The I/O interface requests DMAC for an DMA operation.
2. DMAC sends hold signal to the processor requesting for the data and address bus
3. The processor sends the hold acknowaldge signal to the DMAC indicating the data and address bus were given.
4. DMAC send the address of the data to the address bus
5. Then DMAC requests I/O interface for the data
6. Data recieved is sent to the data bus
7. DMAC latches the interface
8. Sends hold low signal to drop the hold cycle to the processor
9. Processor drops the HLDA signal
10. Increases the address register by one 
11. Increases the Program counter by one  

DMAC uses two signals for requesting and acknowladging the DMA operations:

HOLD: If active, indicates the data bus and address bus were given to the DMAC and the processor is in hold.

HLDA: If active, indicates the processor that the DMA operation is active.

DMAC allows different types of data transfer processes,

Cycle steal:

DMAC can use the data bus either when the Processor is not using it or it can force the CPU to suspend it's current operation and use the data bus. The Latter method is called cycle stealing. Note: Cycle Stealing can be only done in certain break points in the instruction cycle.

Brust Transfer:

In brust mode, the DMAC forces the operations of Processor to be halted for the duration of data transfer.

Hidden DMA:

DMAC allows Hidden DMA operation as well. DMAC monitor's every execution of the processor's instruction and when it reconizes that there is an instruction with sufficient empty clock cycle for a byte of data transfer, it waits until the processor is decoding the opcode then grabs the bus for the data transfer...